The integration of hundreds of millions of circuit elements, such as transistors, on a single integrated circuit necessitates further dramatic scaling down or micro-miniaturization of the physical dimensions of circuit elements, including interconnection structures. Micro-miniaturization has engendered a dramatic increase in transistor engineering complexity, such as the inclusion of lightly doped drain structures, multiple implants for source/drain regions, silicidation of gates and source/drains, and multiple sidewall spacers, for example.
The drive for high performance requires high speed operation of microelectronic components requiring high drive currents in addition to low leakage, i.e., low off-state current, to reduce power consumption. Typically, the structural and doping parameters tending to provide a desired increase in drive current adversely impact leakage current.
Metal gate electrodes have evolved for improving the drive current by reducing polysilicon depletion. However, simply replacing polysilicon gate electrodes with metal gate electrodes may engender issues in forming the metal gate electrode prior to high temperature annealing to activate the source/drain implants, as at a temperature in excess of 900° C. This fabrication technique may degrade the metal gate electrode or cause interaction with the gate dielectric, thereby adversely impacting transistor performance.
Replacement gate techniques have been developed to address problems attendant upon substituting metal gate electrodes for polysilicon gate electrodes. For example, a polysilicon gate is used during initial processing until high temperature annealing to activate source/drain implants has been implemented. Subsequently, the polysilicon is removed and replaced with a metal gate.
Additional issues arise with lateral scaling, such as the formation of contacts. For example, once the contacted poly pitch gets to about 80 nanometers (nm), there is not enough room to land a contact between the gate lines and still maintain good electrical isolation properties between the gate line and the contact. Self aligned contact (SAC) methodology has been developed to address this problem. However, conventional SAC approaches involve metalizing the gate prior to patterning, followed by covering the gate with a hardmask to isolate the gate line from the contact during the contact etch and fill process. This approach, however, is not compatible with the replacement gate process.
A need therefore exists for methodology enabling the fabrication of semiconductor devices comprising integrating both metal replacement gates and self aligned contacts.